1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device mounting a DMOS (Double diffusion Metal Oxide Semiconductor) transistor and a bipolar transistor in a mixed manner, and a method of manufacturing the same.
2. Description of the Background Art
A semiconductor device having a DMOS transistor and a bipolar transistor mounted in a mixed way has been disclosed in Japanese Patent Laying-Open No. 8-321556, for example. Hereinafter, a technique disclosed in the document will be described as an example of a conventional semiconductor device and a manufacturing method thereof, particularly focusing on a high voltage DMOS transistor and an npn bipolar transistor.
FIGS. 14A and 14B are cross sectional views schematically showing a configuration of a conventional semiconductor device.
Referring to FIGS. 14A and 14B, regions RA and RB are regions for forming a high voltage DMOS transistor and a low voltage DMOS transistor, respectively. A region RC is a CMOS (Complementary Metal Oxide Semiconductor) transistor forming region. Regions RD and RE are npn type and pnp type bipolar transistors forming regions, respectively, and a region RF is an EEPROM (Electrically Erasable Programmable Read Only Memory) cell forming region.
In high voltage DMOS transistor region RA, a high voltage n type well region 144 is formed on a p type substrate 141, with an n+ region 142 interposed therebetween.
On the surface of high voltage n type well region 144, a p type region 101 consisting of a relatively deeply formed p type body region 101b and a relatively shallowly formed p type channel region 101a is formed. In p type region 101, an n type source region 102 is formed. A gate electrode layer 106 is formed opposite to p type region 101 that is sandwiched between high voltage n type well region 144 and n type source region 102, with a gate insulating layer 105 interposed therebetween. Gate electrode layer 106 has an end portion extending to overlay a field oxide film 151, and has side surfaces each covered with a respective sidewall insulating layer 107.
In npn bipolar transistor region RD, a high voltage n type well region 144 and an n+ buried region 114 are formed on p type substrate 141, with an n+ region 142 interposed therebetween. On the surface of high voltage n type well region 144, a p type base region 111 consisting of a relatively shallowly formed p type region 111a and a relatively deeply formed p type body region 111b is formed. An n+ emitter region 112 is formed in p type base region 111. An n+ collector contact region 114 is formed on the surface of n+ buried region 114.
Note that high voltage DMOS transistor region RA and npn bipolar transistor region RD, for example, are electrically isolated from other element forming regions by p type isolating regions 143, p type well regions 145a, upper region isolating regions 145b, and field oxide films 151.
Next, a method of manufacturing p type region 101 of the high voltage DMOS transistor and base region 111 of the npn bipolar transistor in this semiconductor device will be described.
FIGS. 15A, 15B, 16A and 16B are simplified cross sectional views showing, in the order of process steps, a method of manufacturing the conventional semiconductor device. Referring first to FIGS. 15A and 15B, a photoresist 161 is patterned by normal photolithography, and using the resist pattern 161 as a mask, a polycrystalline silicon (polysilicon) layer 171 is subjected to etching, to selectively expose the substrate surface. A p type dopant, e.g., boron, is ion implanted into thus exposed regions at 150 to 250 keV, substantially at a right angle with respect to the substrate surface. Accordingly, a p type body region 101b is formed in high voltage DMOS transistor region RA, and a p type body region 111b is formed in npn bipolar transistor region RD. Thereafter, resist pattern 161 is completely removed.
Referring to FIGS. 16A and 16B, a p type dopant, e.g., boron, is again implanted into the regions exposed from polysilicon layer 161 at about 150 keV, at an angle of about 30xc2x0 to 45xc2x0 with respect to the perpendicular of the substrate surface. Accordingly, a p type channel region 101a is formed in high voltage DMOS transistor region RA, and a p type region 111a is formed in npn bipolar transistor region RD. Thus, p type channel region 101a and p type body region 101b constitute a p type region 101 in high voltage DMOS transistor region RA, and p type region 111a and p type body region 111b constitute a p type base region 111 in npn bipolar transistor region RD.
Thereafter, a gate electrode layer is formed by patterning polysilicon layer 171, a sidewall insulating layer 107 is formed to cover sidewalls of the gate electrode layer, and n type source region 102, n+ emitter region 112 and others are formed. The semiconductor device as shown in FIGS. 14A and 14B is thus completed.
The above-described conventional semiconductor device and the manufacturing method thereof, however, suffer from problems that the threshold voltage Vth of the DMOS transistor is hard to control freely, and that a rapidly operating npn bipolar transistor is difficult to realize. These will now be described in detail.
In the conventional manufacturing method, as shown in FIGS. 16A and 16B, an impurity is ion implanted using as a mask polysilicon layer 171 that is to be a gate electrode, to form p type channel region 101a in high voltage DMOS transistor region RA. Since heat treatment causes this p type channel region 101a to diffuse, its end portion SB at the substrate surface extends to directly beneath the gate electrode layer 106, as shown in FIG. 17.
An overlapping length L0 of p type channel region 101a and p type body region 101b in the channel region posed between n type source region 102 and high voltage n type well region 144 thus becomes long. Accordingly, it is almost impossible to control the threshold voltage Vth of high voltage DMOS transistor independently and solely by p type channel region 101a. The longer the overlapping length L0, the more difficult to control the threshold voltage Vth.
As an approach to realize a rapidly operating bipolar transistor, there is a technique to narrow the width (so-called base width) W of base region 111 directly beneath n+ emitter region 112, as shown in FIG. 18. To decrease base width W, it is necessary to make p type region 111b of high concentration so as to increase a breakdown voltage of base region 111. When making p type region 111b of high concentration, however, p type body region 101b shown in FIG. 17, that is to be formed at the same time as p type region 111b, also becomes of high concentration. Such high concentration p type body region 101b leads to longer diffusion length of the impurity within p type body region 101b, and hence, longer overlapping length L0 of p type channel region 101a and p type body region 101b. Therefore, it becomes still more difficult to control the threshold voltage Vth of the DMOS transistor.
In other words, in order to allow easy control of the threshold voltage Vth of DMOS transistor, base width W of the npn bipolar transistor should be made sufficiently large. This, however, makes difficult to realize an npn bipolar transistor that can operate at high speed.
An object of the present invention is to provide a semiconductor device which permits easy control of the threshold voltage Vth of DMOS transistor and facilitates realization of a rapidly operating bipolar transistor, and a manufacturing method thereof.
The semiconductor device according to the present invention is specifically a semiconductor device having an insulated gate type field effect transistor, which includes: a semiconductor substrate; a gate electrode layer of the insulated gate type field effect transistor; a sidewall insulating layer; a first impurity region of the second conductivity type; a second impurity region of the second conductivity type; and a third impurity region of the first conductivity type. The semiconductor substrate includes a main surface and a region of the first conductivity type. The gate electrode layer is formed on the main surface of the semiconductor substrate, with a gate insulating layer interposed therebetween. The sidewall insulating layer is formed to cover a sidewall of the gate electrode layer. The first impurity region is formed in the region of the first conductivity type, and has a portion located at the main surface exposed from the gate electrode layer and the sidewall insulating layer, and has its end portion at the main surface extending to the region directly beneath the gate electrode layer. The second impurity region has a portion located at the main surface exposed from the gate electrode layer and the sidewall insulating layer, has its end portion at the main surface located directly beneath the sidewall insulating layer, and is formed with a diffusion depth that is deeper from the main surface than the first impurity region and to have a portion overlapping the first impurity region. The third impurity region, that is to become either one of source and drain regions of the insulated gate type field effect transistor, is formed at the main surface within the first and second impurity regions so as to sandwich the first impurity region located directly beneath the gate electrode layer between the region of the first conductivity type and the third impurity region.
In the semiconductor device according to the present invention, the second impurity region has an end portion at the main surface located directly beneath the sidewall insulating layer, instead of extending to the region underneath the gate electrode layer as in the conventional example. Therefore, it becomes possible to shorten the overlapping length of, or even eliminate the overlapping portion of, the first and second impurity regions in the channel region of the insulated gate type field effect transistor. Accordingly, it becomes easy to control the threshold voltage of the insulated gate type field effect transistor solely by the first impurity region, thus simplifying the control of threshold voltage.
Preferably, the above semiconductor device is further provided with a bipolar transistor having a base region. The base region includes first and second base regions of the second conductivity type. The first base region is formed at the main surface, in the same manufacturing step as the first impurity region. The second base region is formed at the main surface in the same manufacturing step as the second impurity region, and has a portion overlapping the first base region.
Since the overlapping length of the first and second impurity regions can be shortened as described above, the threshold voltage of the insulated gate type field effect transistor can be easily controlled even when the second impurity region is formed of high concentration. Therefore, the second base region that is formed in the same manufacturing step as the second impurity region can also be formed with high concentration, thereby ensuring a large breakdown voltage of the base region. Accordingly, the second base region can be made shallow, and the width (so-called base width) of the second base region directly beneath the first base region can be decreased. It thus becomes possible to make the bipolar transistor operate at high speed.
Preferably, the above semiconductor device is further provided with an element separating insulating layer formed at the main surface of the semiconductor substrate, and one end of the gate electrode layer overlays the element separating insulating layer.
Accordingly, the insulated gate type field effect transistor can be made to be a high breakdown voltage transistor.
In the above semiconductor device, the gate electrode layer preferably includes a configuration in which a polysilicon layer doped with an impurity and a silicide layer are stacked one on top of the other.
Accordingly, it becomes possible to reduce resistance of the gate electrode layer.
The manufacturing method of the semiconductor device according to the present invention is specifically a method of manufacturing a semiconductor device having an insulated gate type field effect transistor and a bipolar transistor, which includes the following steps.
A region of the first conductivity type is first formed within a semiconductor substrate in an insulated gate type field effect transistor region. A gate electrode layer is then formed on the main surface of the semiconductor substrate within the insulated gate type field effect transistor region, with a gate insulating layer interposed therebetween. The second conductivity type impurity is then selectively introduced into the main surface of the semiconductor substrate by rotational oblique ion implantation, to form, in the insulated gate type field effect transistor region, a first impurity region of the second conductivity type, which has a portion located at the main surface exposed from the gate electrode layer and has its end portion at the main surface extending to the region directly beneath the gate electrode layer, and to form, in the bipolar transistor region, a first base region of the second conductivity type at the main surface. A sidewall insulating layer is then formed to cover a sidewall of the gate electrode layer. The second conductivity type impurity is selectively introduced into the main surface of the semiconductor substrate, substantially at a right angle with respect to the main surface to form, in the insulated gate type field effect transistor region, a second impurity region of the second conductivity type, which has a portion located at the main surface exposed from the gate electrode layer and the sidewall insulating layer, has its end portion at the main surface located directly beneath the sidewall insulating layer, and is formed with a diffusion depth deeper from the main surface than the first impurity region and to have a portion overlapping the first impurity region, and to form, in the bipolar transistor region, a second base region of the second conductivity type, which is formed with a diffusion depth that is deeper from the main surface than the first base region and to have a portion overlapping the first base region. A third impurity region of the first conductivity type, that is to become either one of source and drain regions of the insulated gate type field effect transistor, is formed at the main surface within the first and second impurity regions, to cause the first impurity region located directly beneath the gate electrode layer to be sandwiched between the region of the first conductivity type and the third impurity region.
In the manufacturing method of the semiconductor device according to the present invention, the end portion of the second impurity region at the main surface is located directly beneath the sidewall insulating layer, instead of extending to the region underneath the gate electrode layer as in the conventional example. Therefore, the overlapping length of the first and second impurity regions in the channel region can be made shorter, or, the overlapping portion thereof can even be eliminated. Accordingly, it becomes easy to control the threshold voltage of insulated gate type field effect transistor solely by the first impurity region, thereby simplifying the control of threshold voltage.
Since the overlapping length of the first and second impurity regions can be made shorter, the threshold voltage of the insulated gate type field effect transistor can be controlled easily, even when the second impurity region is formed of high concentration. Therefore, the second base region that is to be formed in the same manufacturing step as the second impurity region can also be made of high concentration, thereby ensuring a large breakdown voltage of the base region. Accordingly, the second base region can be formed shallower to decrease the width (so-called base width) of second base region directly beneath the first base region. This helps speed up the operation of bipolar transistor.
Preferably, in the above manufacturing method of the semiconductor device, the step of introducing the impurity by rotational oblique ion implantation is performed by introducing the impurity at an angle between 45xc2x0 and 60xc2x0 with respect to the perpendicular of the main surface. In the step of introducing the impurity substantially at a right angle with the main surface, the impurity is introduced at an angle between 0xc2x0 to 10xc2x0 with respect to the perpendicular of the main surface.
Accordingly, the first and second impurity regions can be formed in more appropriate positions.
Preferably, the above manufacturing method of the semiconductor device further includes the step of forming an element separating insulating layer at the main surface of the semiconductor substrate, and the gate electrode layer is formed to have one end portion overlaying the element separating insulating layer.
Accordingly, the insulated gate type field effect transistor can be made to be a transistor of high breakdown voltage.
Preferably, in the above method of manufacturing the semiconductor device, the gate electrode layer is formed to have a configuration with a polysilicon layer doped with an impurity and a silicide layer stacked one on top of the other.
Accordingly, resistance of the gate electrode layer can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.